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CML -755-27 Datasheet, PDF

Search Description : 'CML -755-27 ' - Total: 169 (1/9) Pages
Electronic ManufacturerPart NumberDatasheetElectronics Description

Cypress Semiconductor
CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer

Micrel Semiconductor
SY58016L 3.3V 10Gbps DIFFERENTIAL CML LINE DRIVER/RECEIVER WITH INTERNAL TERMINATION
SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input
SY88843V 3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD
SY54016R Low Voltage 1.2V/1.8V CML Differential Line Driver/Receiver with Fail Safe Input 3.2Gbps, 2.5GHz
SY58011U_08 7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION

ON Semiconductor
NB7L111M 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output
NBSG16M_06 2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

National Semiconductor
DS42MB200_07 Dual 4.25 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization

ON Semiconductor
NB7VQ1006M 1.8V / 2.5V 10Gbps Equalizer Receiver with 1:6 Differential CML Outputs

Micrel Semiconductor
SY54011R_10 Low Voltage 1.2V/1.8V CML 1:2 Fanout Buffer, 3.2Gbps, 3.2GHz
SY58606U 4.25Gbps Precision, 1:2 CML Fanout Buffer with Internal Termination and Fail Safe Input
SY88289AL 3.3V, 3.2Gbps CML Low-Power Limiting Post Amplifier with TTL Loss-of-Signal
SY88289CL 3.3V, 3.2Gbps CML Limiting Post Amplifier with High-Gain TTL Loss-of-Signal

ON Semiconductor
NB7V586M 1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator

Micrel Semiconductor
SY88303BL 3.3V, 3.2Gbps CML Limiting Post Amplifier with Wide Loss-of-Signal Detection Range
SY88343HL 3.3V, 3.2Gbps CML Limiting Post Amplifier with High-Gain TTL Loss-of-Signal
SY58024U_07 ULTRA-LOW JITTER DUAL 2 × 2 CROSSPOINT SWITCH w/ CML OUTPUTS AND INTERNAL I/O TERMINATION
SY58028U ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND INTERNAL I/O TERMINATION
SY58034U 6GHz, 1:6 CML FANOUT BUFFER WITH 2:1 MUX INPUT AND INTERNAL I/O TERMINATION

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