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18-MBIT Datasheet, PDF

Search Description : '18-MBIT' - Total: 106 (1/6) Pages
Electronic ManufacturerPart NumberDatasheetElectronics Description

Cypress Semiconductor
CY7C1146V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1311KV18_12 18-Mbit QDR® II SRAM Four-Word Burst Architecture
CY7C1161KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1141V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1303CV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
CY7C1381DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)
CY7C2163KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
CY7C1146KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1387D 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1381CV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D_07 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1370KV33 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
CY7C1380CV25_04 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1371D_12 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
CY7C11661KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1305AV25 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1380DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1370KV25 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
CY7C1371DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture

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