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TRANSFERS Datasheet, PDF

Search Description : 'TRANSFERS' - Total: 20 (1/1) Pages
Electronic ManufacturerPart NumberDatasheetElectronics Description

Winbond
W972GG6JB-25 Double Data Rate architecture: two data transfers per clock cycle

Texas Instruments
DS92UT16 UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

Elite Semiconductor Mem...
M13S128168A-2N Double-data-rate architecture, two data transfers per clock cycle

ATMEL Corporation
AT91SAM9R64_14 Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

Winbond
W9412G2IB4 Double Data Rate architecture; two data transfers per clock cycle

Elite Semiconductor Mem...
M13S128324A-2M Double-data-rate architecture, two data transfers per clock cycle

ATMEL Corporation
AT91SAM9RL64_14 Multi-layer AHB Bus Matrix for Large Bandwidth Transfers

Winbond
W9412G6JH-5 Double Data Rate architecture; two data transfers per clock cycle

National Semiconductor ...
DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

Elite Semiconductor Mem...
M13S2561616A-2A Double-data-rate architecture, two data transfers per clock cycle
M13L32321A-2G Double-data-rate architecture, two data transfers per clock cycle

Winbond
W9725G6JB25I Double Data Rate architecture: two data transfers per clock cycle

Texas Instruments
DS92UT16 DS92UT16TUF UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers

Elite Semiconductor Mem...
M13S2561616A-2S Double-data-rate architecture, two data transfers per clock cycle
M13L2561616A-2A Double-data-rate architecture, two data transfers per clock cycle

Winbond
W9751G6KB-25 Double Data Rate architecture: two data transfers per clock cycle
W631GG6KB-15 Double Data Rate architecture: two data transfers per clock cycle

Elite Semiconductor Mem...
M13S5121632A-2S Double-data-rate architecture, two data transfers per clock cycle
M13S64164A-2Y Double-data-rate architecture, two data transfers per clock cycle

Epson Company
S1R72C05 Support for control, bulk, interrupt, and isochronous transfers

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