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ARCHITECTURE Datasheet, PDF

Search Description : 'ARCHITECTURE' - Total: 515 (1/26) Pages
Electronic ManufacturerPart NumberDatasheetElectronics Description

Cypress Semiconductor
CY7C1510KV18_11 72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses
CY7C1317KV18_1106 18-Mbit DDR II SRAM Four-Word Burst Architecture 333-MHz clock for high bandwidth

Freescale Semiconductor...
MPC5121E_10 e300 Power Architecture processor core

Cypress Semiconductor
CY7C1516KV18_09 72-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1422JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture
CY7C1311CV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture
CY7C1302DV25_06 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
CY7C1350G_06 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
CY7C1261V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1351 128Kx36 Flow-Through SRAM with NoBL TM Architecture
CY7C1310BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C13201KV18 18-Mbit DDR II SRAM 2-Word Burst Architecture

Micross Components
MYX4DDR364M16JT 8n-bit prefetch architecture

Integrated Device Techn...
89HPES22H16 Low-latency cut-through switch architecture

ATMEL Corporation
ATTINY2313V_14 AVRHigh-performance and Low-power RISC Architecture

Cypress Semiconductor
CY7C1566V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1310BV18_07 18-Mbit QDR™-II SRAM 2 Word Burst Architecture
CY7C1161V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1460AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

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