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CLOCK Datasheet, PDF

Search Description : 'CLOCK' - Total: 14 (1/1) Pages
Electronic ManufacturerPart NumberDatasheetElectronics Description
Company Logo Img
Elite Semiconductor Mem...
M13L2561616A-2A Datasheet pdf image
1Mb / 49P
Double-data-rate architecture, two data transfers per clock cycle
M14D1G1664A-2S Datasheet pdf image
707Kb / 65P
Internal pipelined double-data-rate architecture; two data access per clock cycle
M13S128324A-2M Datasheet pdf image
1Mb / 48P
Double-data-rate architecture, two data transfers per clock cycle
M13S128168A-2N Datasheet pdf image
720Kb / 49P
Double-data-rate architecture, two data transfers per clock cycle
M14D2561616A-2E Datasheet pdf image
1Mb / 61P
Internal pipelined double-data-rate architecture; two data access per clock cycle
M13S5121632A-2S Datasheet pdf image
705Kb / 48P
Double-data-rate architecture, two data transfers per clock cycle
M14D128168A Datasheet pdf image
786Kb / 59P
Internal pipelined double-data-rate architecture; two data access per clock cycle
M13S64164A-2Y Datasheet pdf image
1Mb / 49P
Double-data-rate architecture, two data transfers per clock cycle
M13S2561616A-2A Datasheet pdf image
1Mb / 49P
Double-data-rate architecture, two data transfers per clock cycle
M13L32321A-2G Datasheet pdf image
1Mb / 48P
Double-data-rate architecture, two data transfers per clock cycle
M14D1G1664A-2D Datasheet pdf image
724Kb / 64P
Internal pipelined double-data-rate architecture; two data access per clock cycle
M14D5121632A-2K Datasheet pdf image
753Kb / 64P
Internal pipelined double-data-rate architecture; two data access per clock cycle
M13S2561616A-2S Datasheet pdf image
1Mb / 49P
Double-data-rate architecture, two data transfers per clock cycle
M14D128168A-2M Datasheet pdf image
1,023Kb / 59P
Internal pipelined double-data-rate architecture; two data access per clock cycle

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