CML Datasheet(PDF) - SY58025U_07 - Micrel Semiconductor

Manufacturer	Part #	Datasheet	Description
Micrel Semiconductor	SY58025U	225Kb/11P	ULTRA PRECISION DUAL 2:1 CML MUX WITH INTERNAL I/O TERMINATION
	SY58031U	562Kb/9P	ULTRA-PRECISION 1:8 CML fanout buffer WITH INTERNAL I/O TERMINATION
	SY58020U	120Kb/9P	6GHz, 1:4 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
	SY88823V	122Kb/11P	3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER W/TTL SD
	SY58020U	131Kb/9P	6GHz, 1:4 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
	SY58040U	120Kb/11P	ULTRA PRECISION 4 X 4 CML SWITCH WITH INTERNAL I/O TERMINATION
MTRONPTI	M63001GBFPN	624Kb/3P	5x7 mm, 1.8/2.5/3.3 V, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO
Micrel Semiconductor	SY56023R	508Kb/12P	Low Voltage 1.2V/1.8V/2.5V CML 2x2 Crosspoint Switch 6.4Gbps with Equalization
ON Semiconductor	NB6L14M	154Kb/11P	2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer December, 2006 ??Rev. 0
Micrel Semiconductor	SY88315BL	397Kb/10P	3.3V, 3.2Gbps CML Low-Power Limiting Post Amplifier w/TTL Signal Detect
	SY88883V	77Kb/8P	3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER WITH TTL SD
	SY56023R	499Kb/12P	Low Voltage 1.2V/1.8V/2.5V CML 2x2 Crosspoint Switch 6.4Gbps with Equalization
	SY58024U_0708	142Kb/11P	ULTRA-LOW JITTER DUAL 2 횞 2 CROSSPOINT SWITCH w/ CML OUTPUTS
ON Semiconductor	NBSG16M	81Kb/12P	2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2004 ??Rev. 3
Micrel Semiconductor	SY88843V	123Kb/11P	3.3V/5V 3.2Gbps CML LOW-POWER LIMITING POST AMPLIFIER w/TTL SD
	SY58031U	610Kb/8P	ULTRA-PRECISION 1:8 CML FANOUT BUFFER WITH INTERNAL I/O TERMINATION
	SY58011U	200Kb/9P	7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
ON Semiconductor	NB7N017M	139Kb/19P	3.3V SiGe 8?묪it Dual Modulus Programmable Divider/Prescaler with CML Outputs February, 2006 ??Rev. 2
	NB6L295M	199Kb/13P	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs March, 2012 ??Rev. 5
	NB6L295MMNGEVB	199Kb/13P	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs March, 2012 ??Rev. 5

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