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LATENCY Datasheet, PDF |
Searched Keyword : 'LATENCY' - Total: 77 (1/4) Pages |
Manufacturer | Part # | Datasheet | Description |
Cypress Semiconductor |
CY7C1541KV18 |
691Kb/27P |
72-Mbit QDR짰II+ SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency) |
CY7C1166KV18 |
874Kb/29P |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C11611KV18 |
881Kb/29P |
18-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1561V18 |
676Kb/28P |
72-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1546KV18 |
959Kb/31P |
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C15632KV18 |
783Kb/30P |
72-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1648KV18 |
857Kb/30P |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1141V18 |
1Mb/28P |
18-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1246V18 |
1Mb/27P |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1161V18 |
1Mb/29P |
18-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1241V18 |
1Mb/28P |
36-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1546V18 |
1Mb/27P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1566V18 |
1Mb/27P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C11461KV18 |
854Kb/29P |
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1146KV18 |
885Kb/29P |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1246KV18 |
913Kb/28P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1143KV18 |
619Kb/29P |
18-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C12411KV18 |
896Kb/29P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C12611KV18 |
897Kb/30P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) | |
CY7C1561KV18 |
856Kb/29P |
72-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
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