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LATENCY Datasheet, PDF |
Searched Keyword : 'LATENCY' - Total: 229 (10/12) Pages |
Manufacturer | Part # | Datasheet | Description |
Cypress Semiconductor |
CY7C1263XV18 |
1Mb/30P |
36-Mbit QDR짰 II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1563XV18 |
1Mb/29P |
72-Mbit QDR짰 II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) | |
CY7C1268XV18 |
900Kb/28P |
36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | |
Renesas Technology Corp |
RMQSAA3636DGBA |
363Kb/30P |
36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency) May 25, 2015 |
UPD48011318 |
1Mb/51P |
1.1G-BIT L ow Latency DRAM-III Common I/O Burst Length of 2 Feb 01, 2013 |
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R1QLA4436RBG |
955Kb/31P |
144-Mbit DDR?줚I+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT | |
Cypress Semiconductor |
CY7C2245KV18 |
841Kb/28P |
36-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
CY7C2268KV18 |
874Kb/31P |
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | |
CY7C25632KV18 |
496Kb/31P |
72-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | |
CY7C2168KV18 |
879Kb/29P |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | |
CY7C2644KV18 |
840Kb/30P |
144-Mbit QDR짰 II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT | |
Renesas Technology Corp |
R1QKA4436RBG |
967Kb/31P |
144-Mbit QDR?줚I+ SRAM 4-word Burst Architecture(2.0 Cycle Read latency) with ODT |
RMQSDA3636DGBA |
898Kb/31P |
36-Mbit QDR??II+ SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT | |
Cypress Semiconductor |
CY7C2163KV18 |
874Kb/30P |
18-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
CY7C2268KV18 |
876Kb/29P |
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | |
Renesas Technology Corp |
RMQCLA3636DGBA |
885Kb/31P |
36-Mbit DDR??II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT |
RMQSKA3636DGBA |
896Kb/31P |
36-Mbit QDR??II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT | |
Cypress Semiconductor |
CY7C2663KV18 |
871Kb/31P |
144-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Texas Instruments |
DP83620 |
1Mb/105P |
Deterministic, Low Transmit and Receive Latency, Selectable Frequency Synchronized Clock Output, Dynamic Link Quality Monitoring |
Cypress Semiconductor |
CY7C2670KV18 |
824Kb/30P |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
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